To minimize microelectronic circuit delay caused by parasitic capacitance occurring in Back-End-Of-Line (BEOL) interconnects, conventional SiO2 dielectric (dielectric constant k˜4.0) has been replaced with lower-k films (k<3.0). For further performance improvement, aggressive reduction in parasitic capacitance is necessary. Currently, to accommodate microelectronic circuit speeds in the multiple GHz range, the dielectric constant is targeted at less than about 2.2.
Lowering parasitic capacitance can be achieved with new porous low-k dielectrics; however, most of the porous materials have relatively weak mechanical properties as compared to denser dielectrics. It is also a significant challenge to integrate these materials with other BEOL module processes. For example, the conventional chemical-mechanical polish (or CMP) process has difficulty in polishing porous dielectrics, and the conventional plasma vapor deposition (or PVD) of a diffusion barrier layer cannot offer reasonable coverage on the surface of porous dielectrics.
Accordingly, it would be desirable to overcome the limitations of prior art approaches.